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CS4382
114 dB, 192 kHz 8-Channel D/A Converter
Features
24-bit Conversion Up to 192 kHz Sample Rates 114 dB Dynamic Range -100 dB THD+N Supports PCM and DSD Data Formats Selectable Digital Filters Volume Control with Soft Ramp - 1 dB Step Size - Zero Crossing Click-Free Transitions Dedicated DSD Inputs Low Clock-Jitter Sensitivity Simultaneous Support for Two Synchronous Sample Rates for DVD Audio C or Stand-Alone Operation
I
D S D _ S C L K (M 3 )
S C L /C C L K (M 1 ) S D A /C D IN (M 2 ) A D 0 /C S (M 0 ) V L C
Description
The CS4382 is a complete 8-channel digital-to-analog system including digital interpolation, fifth-order deltasigma digital-to-analog conversion, digital de-emphasis, volume control and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter. The CS4382 is available in a 48-pin LQFP package in Commercial grade (-10C to +70C). The CDB4382 Customer Demonstration Board is also available for device evaluation and implementation suggestions. Please see "Ordering Information" on page 42 for complete details. The CS4382 accepts PCM data at sample rates from 4 kHz to 192 kHz, DSD audio data, and operates over a wide power supply range. These features are ideal for multi-channel audio systems including DVD players, SACD players, A/V receivers, digital TV's, mixing consoles, effects processors, and automotive audio systems.
M UTEC1
M U TEC234
RST
C o n tro l P o rt(S ta n d -A lo n e M o d e S e le c t)
E xte rn a l M u te C o n tr o l
V LS
S C LK1
V o lu m e C o n t ro l
I n t e r p o l a t i o n F i lt e r
D AC
A n a lo g F i lt e r
A O U T A 1+ A O U T A1-
M ixer
L RC K1
S CLK 2
L RCK2
S e ri a l P o r t
V o lu m e C o n tr o l
I n t e r p o l a t i o n F i lt e r
DAC
A n a lo g F i lt e r
A O U T B 1+ A O U T B1A O U T A 2+ A O U T A2A O U T B 2+ A O U T B2A O U T A 3+ A O U T A3-
V o lu m e C o n tr o l
I n t e r p o l a t i o n F i lt e r
DAC
A n a lo g F i lt e r
SD IN1
SD I N2
SD I N3
SD IN4
M ixer
V o lu m e C o n tr o l
I n t e r p o l a t i o n F i lt e r
DAC
A n a lo g F i lt e r
V o lu m e C o n tr o l
M ixer
V o lu m e C o n tr o l
I n t e r p o l a t i o n F i lt e r
DAC
A n a lo g F i lt e r
I n t e r p o l a t i o n F i lt e r
DAC
A n a lo g F i lt e r
A O U T B 3+ A O U T B3-
M C LK
V o lu m e C o n tr o l I n t e r p o l a t i o n F i lt e r
DAC
A n a lo g F i lt e r
A O U T A 4+ A O U T A4A O U T B 4+ A O U T B4-
/2
D SDxx
M ixer
V o lu m e C o n tr o l
8
I n t e r p o l a t i o n F i lt e r
DAC
A n a lo g F i lt e r
VQ F IL T +
VD
GND
GND
VA
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2008 (All Rights Reserved)
FEB '08 DS514F2
CS4382
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 5 ANALOG CHARACTERISTICS............................................................................................................. 5 ANALOG CHARACTERISTICS............................................................................................................. 6 POWER AND THERMAL CHARACTERISTICS ................................................................................... 6 ANALOG FILTER RESPONSE ............................................................................................................. 7 DIGITAL CHARACTERISTICS.............................................................................................................. 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 8 RECOMMENDED OPERATING CONDITIONS .................................................................................... 8 SWITCHING CHARACTERISTICS ....................................................................................................... 9 DSD - SWITCHING CHARACTERISTICS .......................................................................................... 10 SWITCHING CHARACTERISTICS - CONTROL PORT - IC(R) FORMAT ........................................... 11 SWITCHING CHARACTERISTICS - CONTROL PORT - SPITM FORMAT......................................... 12 2. TYPICAL CONNECTION DIAGRAM ............................................................................................... 13 3. REGISTER QUICK REFERENCE ....................................................................................................... 15 4. REGISTER DESCRIPTION ................................................................................................................. 16 4.1 Mode Control 1 (Address 01h) ..................................................................................................... 16 4.1.1 Control Port Enable (CPEN) ............................................................................................ 16 4.1.2 Freeze Controls (FREEZE) .............................................................................................. 16 4.1.3 Master Clock Divide Enable (MCLKDIV) ......................................................................... 16 4.1.4 DAC Pair Disable (DACx_DIS) ........................................................................................ 16 4.1.5 Power Down (PDN) .......................................................................................................... 17 4.2 Mode Control 2 (Address 02h) .................................................................................................... 17 4.2.1 Digital Interface Format (DIF) .......................................................................................... 17 4.2.2 Serial Audio Data Clock Source (SDINXCLK) ................................................................. 18 4.3 Mode Control 3 (Address 03h) .................................................................................................... 18 4.3.1 Soft Ramp and Zero Cross Control (SZC) ....................................................................... 18 4.3.2 Single Volume Control (SNGLVOL) ................................................................................. 19 4.3.3 Soft Volume Ramp-Up After Error (RMP_UP) ................................................................. 19 4.3.4 Mutec Polarity (MUTEC+/-) .............................................................................................. 19 4.3.5 Auto-Mute (AMUTE) ........................................................................................................ 20 4.3.6 Mutec Pin Control (MUTEC) ............................................................................................ 20 4.4 Filter Control (Address 04h) ........................................................................................................ 20 4.4.1 Interpolation Filter Select (FILT_SEL) .............................................................................. 20 4.4.2 De-Emphasis Control (DEM) ........................................................................................... 20 4.4.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) ............................................... 21 4.5 Invert Control (Address 05h) ....................................................................................................... 21 4.5.1 Invert Signal Polarity (INV_XX) ........................................................................................ 21 4.6 Mixing Control Pair 1 (Channels A1 & B1)(Address 06h) Mixing Control Pair 2 (Channels A2 & B2)(Address 09h) Mixing Control Pair 3 (Channels A3 & B3)(Address 0Ch) Mixing Control Pair 4 (Channels A4 & B4)(Address 0Fh) ......................................................... 21 4.6.1 Channel A Volume = Channel B Volume (A=B) ............................................................... 21 4.6.2 ATAPI Channel Mixing and Muting (ATAPI) .................................................................... 22 4.6.3 Functional Mode (FM) ...................................................................................................... 23 4.7 Volume Control (Addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh, 10h, 11h) ...................................... 23 4.7.1 Mute (MUTE) ................................................................................................................... 23 4.7.2 Volume Control (xx_VOL) ................................................................................................ 23 4.8 Chip Revision (Address 12h) ....................................................................................................... 24 4.8.1 Part Number ID (PART) [Read Only] ............................................................................... 24 5. PIN DESCRIPTION .............................................................................................................................. 25 6. APPLICATIONS .................................................................................................................................. 28 6.1 Grounding and Power Supply Decoupling .................................................................................... 28 2 DS514F2
CS4382
6.2 PCM Mode Select ......................................................................................................................... 28 6.3 Recommended Power-Up Sequence ........................................................................................... 28 6.4 Analog Output and Filtering .......................................................................................................... 28 6.5 Interpolation Filter ......................................................................................................................... 28 6.6 Clock Source Selection ................................................................................................................ 29 6.7 Using DSD Mode .......................................................................................................................... 29 7. CONTROL PORT INTERFACE ........................................................................................................... 29 7.1 Enabling the Control Port ............................................................................................................. 30 7.2 Format Selection .......................................................................................................................... 30 7.3 IC Format .................................................................................................................................... 30 7.3.1 Writing in IC Format ........................................................................................................ 30 7.3.2 Reading in IC Format ...................................................................................................... 30 7.4 SPI Format ................................................................................................................................... 30 7.4.1 Writing in SPI ................................................................................................................... 31 7.5 Memory Address Pointer (MAP) .................................................................................................. 31 7.5.1 INCR (Auto Map Increment Enable) ................................................................................ 31 7.5.2 MAP4-0 (Memory Address Pointer) ................................................................................. 32 8. FILTER PLOTS .............................................................................................................................. 33 9. DIAGRAMS ..................................................................................................................... 37 10. PARAMETER DEFINITIONS ............................................................................................................. 40 11. REFERENCES ................................................................................................................................... 40 12. PACKAGE DIMENSIONS ................................................................................................................. 41 13. ORDERING INFORMATION ............................................................................................................. 42 14. REVISION HISTORY ......................................................................................................................... 42
LIST OF FIGURES
Figure 1. Serial Mode Input Timing .............................................................................................................. 9 Figure 2. Direct Stream Digital - Serial Audio Input Timing........................................................................ 10 Figure 3. Control Port Timing - IC Format................................................................................................. 11 Figure 4. Control Port Timing - SPI Format................................................................................................ 12 Figure 5. Typical Connection Diagram Control Port................................................................................... 13 Figure 6. Typical Connection Diagram Stand-Alone .................................................................................. 14 Figure 7. Control Port Timing, IC Format.................................................................................................. 31 Figure 8. Control Port Timing, SPI Format................................................................................................. 31 Figure 9. Single-Speed (fast) Stopband Rejection..................................................................................... 33 Figure 10. Single-Speed (fast) Transition Band ......................................................................................... 33 Figure 11. Single-Speed (fast) Transition Band (detail) ............................................................................. 33 Figure 12. Single-Speed (fast) Passband Ripple ....................................................................................... 33 Figure 13. Single-Speed (slow) Stopband Rejection ................................................................................. 33 Figure 14. Single-Speed (slow) Transition Band........................................................................................ 33 Figure 15. Single-Speed (slow) Transition Band (detail)............................................................................ 34 Figure 16. Single-Speed (slow) Passband Ripple...................................................................................... 34 Figure 17. Double-Speed (fast) Stopband Rejection ................................................................................. 34 Figure 18. Double-Speed (fast) Transition Band........................................................................................ 34 Figure 19. Double-Speed (fast) Transition Band (detail)............................................................................ 34 Figure 20. Double-Speed (fast) Passband Ripple...................................................................................... 34 Figure 21. Double-Speed (slow) Stopband Rejection ................................................................................ 35 Figure 22. Double-Speed (slow) Transition Band ...................................................................................... 35 Figure 23. Double-Speed (slow) Transition Band (detail) .......................................................................... 35 Figure 24. Double-Speed (slow) Passband Ripple .................................................................................... 35 Figure 25. Quad-Speed (fast) Stopband Rejection .................................................................................... 35 Figure 26. Quad-Speed (fast) Transition Band .......................................................................................... 35 Figure 27. Quad-Speed (fast) Transition Band (detail) .............................................................................. 36 DS514F2 3
CS4382
Figure 28. Quad-Speed (fast) Passband Ripple ........................................................................................ 36 Figure 29. Quad-Speed (slow) Stopband Rejection................................................................................... 36 Figure 30. Quad-Speed (slow) Transition Band......................................................................................... 36 Figure 31. Quad-Speed (slow) Transition Band (detail)............................................................................. 36 Figure 32. Quad-Speed (slow) Passband Ripple....................................................................................... 36 Figure 33. Format 0 - Left Justified up to 24-bit Data................................................................................. 37 Figure 34. Format 1 - IS up to 24-bit Data ................................................................................................ 37 Figure 35. Format 2 - Right Justified 16-bit Data ....................................................................................... 37 Figure 36. Format 3 - Right Justified 24-bit Data ....................................................................................... 37 Figure 37. Format 4 - Right Justified 20-bit Data ....................................................................................... 38 Figure 38. Format 5 - Right Justified 18-bit Data ....................................................................................... 38 Figure 39. De-Emphasis Curve.................................................................................................................. 38 Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, 3, or 4) ................................................ 38 Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4) ............................................................... 39 Figure 42. Recommended Output Filter..................................................................................................... 39
LIST OF TABLES
Table 1. Digital Interface Formats - PCM Mode......................................................................................... 17 Table 2. Digital Interface Formats - DSD Mode ......................................................................................... 18 Table 3. ATAPI Decode ............................................................................................................................. 22 Table 4. Example Digital Volume Settings ................................................................................................. 23 Table 5. Common Clock Frequencies........................................................................................................ 27 Table 6. Digital Interface Format, Stand-Alone Mode Options................................................................... 27 Table 7. Mode Selection, Stand-Alone Mode Options ............................................................................... 27 Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options ............................................................ 27
4
DS514F2
CS4382 1. CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS
(Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Test load RL = 3 k, CL = 100 pF, VA = 5 V, VD = 3.3 V (see Figure 5) For Single-Speed Mode, Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz; For Double-Speed Mode, Fs = 96 kHz, SCLK = 6.144 MHz, MCLK = 12.288 MHz; For Quad-Speed Mode, Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz; For Direct Stream Digital Mode, Fs = 128 x 48 kHz, DSD_SCLK = 6.144 MHz, MCLK = 12.288 MHz). Parameters
Specified Temperature Range Dynamic Range (Note 2) unweighted A-Weighted 16-bit unweighted (Note 3) A-Weighted 24-bit (Note 2) THD+N 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB (1 kHz) 24-bit
Symbol
TA
Min
-10 105 108 -
Typ
111 114 94 97 -100 -91 -51 -94 -74 -34 114 90
Max
70 -94 -
Unit
C dB dB dB dB dB dB dB dB dB dB dB dB
CS4382-KQZ Dynamic Performance - All PCM modes and DSD (Note 1)
Total Harmonic Distortion + Noise
16-bit (Note 3) Idle Channel Noise / Signal-to-noise ratio Interchannel Isolation
Notes: 1. CS4382-KQZ parts are tested at 25C. 2. One-half LSB of triangular PDF dither is added to data. 3. Performance limited by 16-bit quantization noise.
DS514F2
5
CS4382 ANALOG CHARACTERISTICS
(Continued) Parameters Analog Output - All PCM modes and DSD
Full Scale Differential Output Voltage Quiescent Voltage Max Current from VQ Interchannel Gain Mismatch Gain Drift Output Impedance AC-Load Resistance Load Capacitance (Note 4)
Symbol
VFS VQ IQMAX
Min
86% VA 3 -
Typ
91% VA 50% VA 1 0.1 100 100 -
Max
96% VA 100
Units
Vpp VDC A dB ppm/C k pF
(Note 4)
ZOUT RL CL
POWER AND THERMAL CHARACTERISTICS
Parameters Power Supplies
normal operation, VA= 5 V VD= 5 V VD= 3.3 V Interface current, VLC=5 V (Notes 6, 7) VLS=5 V power-down state (all supplies) (Note 8) Power Dissipation (Note 5) VA = 5 V, VD = 3.3 V normal operation power-down (Note 8) VA = 5 V, VD = 5 V normal operation power-down (Note 8) Package Thermal Resistance multi-layer dual-layer Power Supply Rejection Ratio (Note 9) (1 kHz) (60 Hz) Power Supply Current (Note 5) IA ID ID ILC ILS Ipd 60 45 30 2 84 200 400 1 525 1 48 65 15 60 40 66 70 46 485 680 mA mA mA A A A mW mW mW mW C/Watt C/Watt C/Watt dB dB
Symbol
Min
Typ
Max
Units
JA JA JC PSRR
Notes: 4. VFS is tested under load RL and includes attenuation due to ZOUT 5. Current consumption increases with increasing FS within a given speed mode and is signal dependant. Max values are based on highest FS and highest MCLK. 6. ILC measured with no external loading on the SDA pin. 7. This specification is violated when the VLC supply is greater than VD and when pin 16 (M1/SDA) is tied or pulled low. Logic tied to pin 16 needs to be able to sink this current. 8. Power Down Mode is defined as RST pin = Low with all clock and data lines held static. 9. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.
6
DS514F2
CS4382 ANALOG FILTER RESPONSE
Fast Roll-Off Slow Roll-Off (Note 10) Parameter Min Typ Max Min Typ Max Combined Digital and On-chip Analog Filter Response - Single-Speed Mode (Note 11)
Passband (Note 12) to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 13) Group Delay Passband Group Delay Deviation 0 - 20 kHz De-emphasis Error (Note 14) Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz Fs = 48 kHz 0.417 0.499 +0.01 6.5/Fs 0.14/Fs 0.23 0.14 0.09 Response - Double-Speed Mode - 96 kHz (Note 11) 0 .430 0 .296 0 .499 0 .499 -0.01 0.01 -0.01 0.01 .583 .792 80 70 4.6/Fs 3.9/Fs 0.03/Fs 0.01/Fs Response - Quad-Speed Mode - 192 kHz (Note 11) 0 .105 0 .104 0 .490 0 .481 -0.01 0.01 -0.01 0.01 .635 .868 90 75 4.7/Fs 4.2/Fs 0.01/Fs 0.01/Fs Response - DSD Mode (Note 11) 0 20 0 120 -.01 0.1 0 0 -0.01 .547 90 12/Fs .454 .499 +0.01 0.41/Fs 0.23 0.14 0.09 0 0 -0.01 .583 64 -
Unit
Fs Fs dB Fs dB s s dB dB dB Fs Fs dB Fs dB s s Fs Fs dB Fs dB s s kHz kHz dB
Combined Digital and On-chip Analog Filter
Passband (Note 12) to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 13) Group Delay Passband Group Delay Deviation 0 - 20 kHz to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 13) Group Delay Passband Group Delay Deviation 0 - 20 kHz
Combined Digital and On-chip Analog Filter
Passband (Note 12)
Combined Digital and On-chip Analog Filter
Passband (Note 12) to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz
Notes: 10. Slow Roll-Off interpolation filter is only available in Control Port Mode. 11. Filter response is not tested but is guaranteed by design. 12. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9 to 32) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 13. Single and Double-Speed Mode Measurement Bandwidth is from stopband to 3 Fs. Quad-Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs. 14. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in StandAlone Mode
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7
CS4382 DIGITAL CHARACTERISTICS
(For KQZ TA = -10C to +70C; VLC = VLS = 1.8 V to 5.5 V) Parameters
High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Maximum MUTEC Drive Current MUTEC High-Level Output Voltage MUTEC Low-Level Output Voltage Serial Data Port Control Port Serial Data Port Control Port (Note 7)
Symbol
VIH VIH VIL VIL Iin
Min
70% VLS 70% VLC -
Typ
8 3 VA 0
Max
20% VLS 20% VLC 10 -
Units
V V V V A pF mA V V
VOH VOL
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to ground.) Parameters
Analog power Digital internal power Serial data port interface power Control port interface power Input Current, Any Pin Except Supplies Digital Input Voltage Serial data port interface Control port interface Ambient Operating Temperature (power applied) Storage Temperature DC Power Supply
Symbol
VA VD VLS VLC Iin VIND-S VIND-C TA Tstg
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 -65
Max
6.0 6.0 6.0 6.0 10 VLS+ 0.4 VLC+ 0.4 125 150
Units
V V V V mA V V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground.) Parameters
DC Power Supply Analog power Digital internal power Serial data port interface power Control port interface power
Symbol
VA VD VLS VLC
Min
4.5 3.0 1.8 1.8
Typ
5.0 3.3 5.0 5.0
Max
5.5 5.5 5.5 5.5
Units
V V V V
8
DS514F2
CS4382 SWITCHING CHARACTERISTICS
(For KQZ TA = -10C to +70C; VLS = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF) Parameters
MCLK Frequency (Note 15) Single-Speed Mode Double-Speed Mode Quad-Speed Mode MCLK Duty Cycle Input Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs tsclkl tsclkh tsclkw tsclkw tslrd tslrs tsdlrs tsdh (Note 17) 1.024 6.400 6.400 40 4 50 100 45 20 20 2 ---------------MCLK 4 ---------------MCLK 20 20 20 20 0.25 50 50 1.00 51.2 51.2 51.2 60 50 100 200 55 4.00 MHz MHz MHz % kHz kHz kHz % ns ns ns ns ns ns ns ns
Symbol
Min
Typ
Max
Units
LRCK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Period (Note 16) SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time LRCK1 to LRCK2 frequency ratio
Notes: 15. See Table 5 on page 27 for suggested MCLK frequencies. 16. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled. 17. The higher frequency LRCK must be an exact integer multiple (1, 2, or 4) of the lower frequency LRCK. .
LRCK t slrd t slrs t sclkl t sclkh
SCLK t sdlrs SDATA t sdh
Figure 1. Serial Mode Input Timing
DS514F2
9
CS4382 DSD - SWITCHING CHARACTERISTICS
(For KQZ TA = -10C to +70C; Logic 0 = GND; VLS = 1.8 V to 5.5 V; Logic 1 = VLS Volts; CL = 30 pF) Parameter
Master Clock Frequency (Note 18) MCLK Duty Cycle (All DSD modes) DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency (64x Oversampled) (128x Oversampled) DSD_L / _R valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_L or DSD_R hold time
Symbol
Min
4.096 40
Typ
50 -
Max
38.4 60 3.2 6.4 -
Unit
MHz % ns ns MHz MHz ns ns
tsclkl tsclkh
tsdlrs tsdh
20 20 1.024 2.048 20 20
Note: 18. Min is 4 times 64x DSD or 2 times 128x DSD, and Max is 12 times 64x DSD or 6 times 128x DSD. The proper MCLK to DSD_SCLK ratio must be set either by the DIF registers or the M0:2 pins
t sclkh t sclkl DSD_SCLK t sdlrs
DSD_L, DSD_R
t sdh
Figure 2. Direct Stream Digital - Serial Audio Input Timing
10
DS514F2
CS4382 SWITCHING CHARACTERISTICS - CONTROL PORT - IC(R) FORMAT
(For KQZ TA = -10C to +70C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF) Parameter
SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 20) (Note 19)
Symbol
fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc, trc tfc, tfc tsusp tack
Min
500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 -
Max
100 1 300 (Note 21)
Unit
kHz ns s s s s s s ns s ns s ns
Notes: 19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed. 21.
15 15 15 -------------------- for Single-Speed Mode, -------------------- for Double-Speed Mode, ----------------- for Quad-Speed Mode. 256 x Fs 128 x Fs 64 x Fs
Note 1
SDA
001100 ADDR AD0 R/W
ACK
DATA 1-8
ACK
DATA 1-8
ACK
SCL
Start
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 3. Control Port Timing - IC Format
DS514F2
11
CS4382 SWITCHING CHARACTERISTICS - CONTROL PORT - SPITM FORMAT
(For KQZ TA = -10C to +70C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF) Parameter
CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 23) (Note 24) (Note 24) (Note 22)
Symbol
fsclk tsrs tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2
Min
500 500 1.0 20 1 ---------------MCLK 1 ---------------MCLK 40 15 -
Max
MCLK ---------------2 100 100
Unit
MHz ns ns s ns ns ns ns ns ns ns
Notes: 22. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 23. Data must be held for sufficient time to bridge the transition time of CCLK. 24. For FSCK < 1 MHz.
RST
t srs
CS t spi t css CCLK t r2
CDIN
t scl
t sch
t csh
t f2
t dsu t dh
Figure 4. Control Port Timing - SPI Format
12
DS514F2
CS4382 2. TYPICAL CONNECTION DIAGRAM
+ 3 .3 V to + 5 V
1 F + 0 .1 F
+5 V
0 .1 F + 1 F
4 VD
32 VA AO UTA1+
39
A O U TA 16 7
40
A n a lo g C o n d itio n in g a n d M u tin g
M C LK
LRC K1 S C LK1
AO UTB1+
38
9
PCM D ig ita l A u d io S o u rc e
A O U TB 1AO UTA2+
37
35
A n a lo g C o n d itio n in g a n d M u tin g
10
12
LRC K2 SCLK2
S D IN 1
S D IN 2 S D IN 3
8
11
A O U TA 2AO UTB2+
A O U TB 2AO UTA3+
36
A n a lo g C o n d itio n in g a n d M u tin g
34
13
33
29
A n a lo g C o n d itio n in g a n d M u tin g
14
S D IN 4
+ 1 .8 V to + 5 V 0 .1 F
43
VLS
A O U TA 3-
30
28
27
A n a lo g C o n d itio n in g a n d M u tin g
CS4382
AO UTB3+
A O U TB 33 2
1
A n a lo g C o n d itio n in g a n d M u tin g
DSDA1 DSDB1 DSDA2
AO UTA4+
25
A O U TA 4AO UTB4+
A O U TB 4-
26
24
23
A n a lo g C o n d itio n in g a n d M u tin g
DSD A u d io S o u rc e
48
47
DSDB2
DSDA3 DSDB3 DSDA4
DSDB4
A n a lo g C o n d itio n in g a n d M u tin g
46
45 44
MUTEC1
M UTEC 234
41
22
M u te D rive
42
D S D_S CLK
19
M ic ro C o n tro lle r
RST S C L /C C L K S D A /C D IN A D O /C S
15 16
17
N o te *
18 0 .1 F
2 K
2 K
F IL T + 2 0
VLC
+ 1 .8 V to + 5 V
VQ
21
0 .1 F + 1 F
+ 0 .1 F
47 F
N o te : N e c e s s a ry fo r I C c o n tro l p o rt o p e ra tio n
2
GND 5
GND 31
Figure 5. Typical Connection Diagram Control Port
DS514F2
13
CS4382
+ 3 .3 V to + 5 V
1 F
47 K
+5 V
+
0 .1 F
4 VD
0 .1 F 32 VA AO UTA1+
AO U TA1-
+
1 F
VLS
N o te D S D
39
40
38
37
A n a lo g C o n d itio n in g a n d M u tin g
6 7
M C LK
LRC K1 SC LK1
LRC K2 SCLK2
AO UTB1+
AO U TB1-
9
PCM D ig ita l A u d io S o u rc e
A n a lo g C o n d itio n in g a n d M u tin g
10
12
8
11
MUTEC1
41
S D IN 1
S D IN 2 S D IN 3
S D IN 4
AO UTA2+
AO U TA2AO UTB2+
M u te D riv e
13
14
35
36
34
33
A n a lo g C o n d itio n in g a n d M u tin g
+ 1 .8 V to + 5 V 0 .1 F
43
VLS
C S 4 3 8 2 AO U TB2AO UTA3+
AO U TA33 2
A n a lo g C o n d itio n in g a n d M u tin g
29
30
28
27
25
26
24
A n a lo g C o n d itio n in g a n d M u tin g
DSDA1 DSDB1 DSDA2
DSDB2
AO UTB3+
AO U TB3AO UTA4+
AO U TA4AO UTB4+
AO U TB4-
1
DSD A u d io S o u rc e 48
A n a lo g C o n d itio n in g a n d M u tin g
47
46
DSDA3 DSDB3 DSDA4
A n a lo g C o n d itio n in g a n d M u tin g
45 44
DSDB4
N o te D S D
23
A n a lo g C o n d itio n in g a n d M u tin g
47 K
42
M 3 (D S D _ S C L K )
M U TE C234
22
M u te D riv e
15
S ta n d -A lo n e M ode C o n fig u ra tio n
M2 M1 M0 RST
16
17 19
N o te V L C
F IL T + 2 0 VQ 21
0 .1 F
+ + 1 F 0 .1 F
47 F
+ 1 .8 V to + 5 V
18 0 .1 F
VLC
GND 5
GND 31
N o te V L C : If s e rie s re s is to rs a re u s e d th e y m u s t b e < 1 k O h m . If p o s s ib le tie V L C to th e V D s u p p ly to re d u c e p o s s ib le e x c e s s c u rre n t c o n s u m p tio n fro m V L C .
N o te D S D : F o r D S D o p e ra tio n : 1 ) L R C K 1 m u s t b e tie d to V L S a n d re m a in s ta tic h ig h . 2 ) M 3 P C M s ta n d -a lo n e c o n fig u ra tio n p in b e c o m e s D S D _ S C L K
Figure 6. Typical Connection Diagram Stand-Alone
14
DS514F2
CS4382 3. REGISTER QUICK REFERENCE
Addr
01h 02h 03h 04h 05h 06h
Function
Mode Control 1 default Mode Control 2 default Mode Control 3 default Filter Control default Invert Control default Mixing Control Pair 1 (AOUTx1) default Vol. Control A1 default Vol. Control B1 default Mixing Control Pair 2 (AOUTx2) default
7
CPEN 0 Reserved 0 SZC1 1 Reserved 0 INV_B4 0 P1_A=B 0 A1_MUTE 0 B1_MUTE 0 P2_A=B 0 A2_MUTE 0 B2_MUTE 0 P3_A=B 0 A3_MUTE 0 B3_MUTE 0 P4_A=B 0 A4_MUTE 0 B4_MUTE 0 PART3 1
6
FREEZE 0 DIF2 0 SZC0 0 Reserved 0 INV_A4 0 P1ATAPI4 0 A1_VOL6 0 B1_VOL6 0 P2ATAPI4 0 A2_VOL6 0 B2_VOL6 0 P3ATAPI4 0 A3_VOL6 0 B3_VOL6 0 P4ATAPI4 0 A4_VOL6 0 B4_VOL6 0 PART2 0
5
0 DIF1 0 SNGLVOL 0 Reserved 0 INV_B3 0 P1ATAPI3 1 A1_VOL5 0 B1_VOL5 0 P2ATAPI3 1 A2_VOL5 0 B2_VOL5 0 P3ATAPI3 1 A3_VOL5 0 B3_VOL5 0 P4ATAPI3 1 A4_VOL5 0 B4_VOL5 0 PART1 1
4
0 DIF0 0 RMP_UP 0 FILT_SEL 0 INV_A3 0 P1ATAPI2 0 A1_VOL4 0 B1_VOL4 0 P2ATAPI2 0 A2_VOL4 0 B2_VOL4 0 P3ATAPI2 0 A3_VOL4 0 B3_VOL4 0 P4ATAPI2 0 A4_VOL4 0 B4_VOL4 0 PART0 0
3
0 0 MUTEC+/0 Reserved 0 INV_B2 0 P1ATAPI1 0 A1_VOL3 0 B1_VOL3 0 P2ATAPI1 0 A2_VOL3 0 B2_VOL3 0 P3ATAPI1 0 A3_VOL3 0 B3_VOL3 0 P4ATAPI1 0 A4_VOL3 0 B4_VOL3 0 Reserved -
2
0 0 AMUTE 1 DEM1 0 INV_A2 0 P1ATAPI0 1 A1_VOL2 0 B1_VOL2 0 P2ATAPI0 1 A2_VOL2 0 B2_VOL2 0 P3ATAPI0 1 A3_VOL2 0 B3_VOL2 0 P4ATAPI0 1 A4_VOL2 0 B4_VOL2 0 Reserved -
1
0 0 Reserved 0 DEM0 0 INV_B1 0 P1FM1 0 A1_VOL1 0 B1_VOL1 0 P2FM1 0 A2_VOL1 0 B2_VOL1 0 P3FM1 0 A3_VOL1 0 B3_VOL1 0 P4FM1 0 A4_VOL1 0 B4_VOL1 0 Reserved -
0
PDN 1 0 MUTEC 0 RMP_DN 0 INV_A1 0 P1FM0 0 A1_VOL0 0 B1_VOL0 0 P2FM0 0 A2_VOL0 0 B2_VOL0 0 P3FM0 0 A3_VOL0 0 B3_VOL0 0 P4FM0 0 A4_VOL0 0 B4_VOL0 0 Reserved -
MCLKDIV DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS
SDIN4CLK SDIN3CLK SDIN2CLK SDIN1CLK
07h 08h 09h
0Ah Vol. Control A2 default 0Bh Vol. Control B2 default 0Ch Mixing Control Pair 3 (AOUTx3) default 0Dh Vol. Control A3 default 0Eh Vol. Control B3 default 0Fh Mixing Control Pair 4 (AOUTx4) default 10h 11h 12h Vol. Control A4 default Vol. Control B4 default Chip Revision default
DS514F2
15
CS4382 4. REGISTER DESCRIPTION
Note: All registers are read/write in IC Mode and write-only in SPI, unless otherwise noted.
4.1
Mode Control 1 (Address 01h)
7 CPEN 0 6 FREEZE 0 5 MCLKDIV 0 4 DAC4_DIS 0 3 DAC3_DIS 0 2 DAC2_DIS 0 1 DAC1_DIS 0 0 PDN 1
4.1.1
Control Port Enable (CPEN)
Default = 0 0 - Disabled 1 - Enabled Function: This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user should write this bit within 10 ms following the release of Reset.
4.1.2
Freeze Controls (FREEZE)
Default = 0 0 - Disabled 1 - Enabled Function: This function allows modifications to be made to the registers without the changes taking effect until the FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then Disable the FREEZE bit.
4.1.3
Master Clock Divide Enable (MCLKDIV)
Default = 0 0 - Disabled 1 - Enabled Function: The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry.
4.1.4
DAC Pair Disable (DACx_DIS)
Default = 0 0 - DAC Pair x Enabled 1 - DAC Pair x Disabled Function: When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state. It is advised that changes to these bits be made while the power-down (PDN) bit is enabled to eliminate the possibility of audible artifacts.
16
DS514F2
CS4382
4.1.5 Power Down (PDN)
Default = 1 0 - Disabled 1 - Enabled Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to `enabled' on power-up and must be disabled before normal operation in Control Port Mode can occur.
4.2
Mode Control 2 (Address 02h)
6 DIF2 0 5 DIF1 0 4 DIF0 0 3 SDIN4CLK 0 2 SDIN3CLK 0 1 SDIN2CLK 0 0 SDIN1CLK 0
7 Reserved 0
4.2.1
Digital Interface Format (DIF)
Default = 000 - Format 0 (Left Justified, up to 24-bit data) Function: These bits select the interface format for the serial audio input. The Functional Mode bits determine whether PCM or DSD Mode is selected. PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 33-38. Note: While in PCM Mode, the DIF bits should only be changed when the power-down (PDN) bit is set to ensure proper switching from one mode to another.
DIF2
0 0 0 0 1 1 1 1
DIF1
0 0 1 1 0 0 1 1
DIF0
0 1 0 1 0 1 0 1
DESCRIPTION Left Justified, up to 24-bit data IS, up to 24-bit data Right Justified, 16-bit data Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 18-bit data Reserved Reserved
Format
0 1 2 3 4 5
FIGURE
33 34 35 36 37 38
Table 1. Digital Interface Formats - PCM Mode
DS514F2
17
CS4382
DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required Master clock to DSD data rate is defined by the Digital Interface Format pins. An additional write of 99h to register 00h and 80h to register 1Ah is required to access the modes denoted with *. DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIFO 0 1 0 1 0 1 0 1 DESCRIPTION 64x oversampled DSD data with a 4x MCLK to DSD data rate 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate Table 2. Digital Interface Formats - DSD Mode Note * * * * * *
4.2.2
Serial Audio Data Clock Source (SDINXCLK)
Default = 0 0 - SDINx clocked by SCLK1 and LRCK1 1 - SDINx clocked by SCLK2 and LRCK2 Function: The SDINxCLK bit specifies which SCLK/LRCK input pair is used to clock in the data on the given SDINx line. For more details see "Clock Source Selection" on page 29.
4.3
Mode Control 3 (Address 03h)
7 SZC1 1 6 SZC0 0 5 SNGLVOL 0 4 RMP_UP 0 3 Reserved 0 2 AMUTE 1 1 Reserved 0 0 MUTEC 0
4.3.1
Soft Ramp and Zero Cross Control (SZC)
Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Immediate Change When Immediate Change is selected all level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
18
DS514F2
CS4382
Soft Ramp Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
4.3.2
Single Volume Control (SNGLVOL)
Default = 0 0 - Disabled 1 - Enabled Function: The individual channel volume levels are independently controlled by their respective Volume Control Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.
4.3.3
Soft Volume Ramp-Up After Error (RMP_UP)
Default = 0 0 - Disabled 1 - Enabled Function: An un-mute will be performed after executing a filter mode change, after a LRCK/MCLK ratio change or error, and after changing the Functional Mode. When this feature is enabled, this un-mute is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate un-mute is performed in these instances. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
4.3.4
Mutec Polarity (MUTEC+/-)
Default = 0 0 - Active High 1 - Active Low Function: The active polarity of the MUTEC pin(s) is determined by this register. When set to 0 (default), the MUTEC pins are high when active. When set to 1 the MUTEC pin(s) are low when active. Note: When the onboard mute circuitry is designed for active low, the MUTEC outputs will be high (unmuted) for the period of time during reset and before this bit is enabled to 1.
DS514F2
19
CS4382
4.3.5 Auto-Mute (AMUTE)
Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits in the Mode Control 3 register.
4.3.6
Mutec Pin Control (MUTEC)
Default = 0 0 - Two Mute control signals 1 - Single mute control signal on MUTEC1 Function: Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to `0', a logical AND of DAC pair 1 mute control signals are output on MUTEC1 and a logical AND of the mute control signals of DAC pairs 2, 3, and 4 are output on MUTEC234. When set to `1', a logical AND of all DAC pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For more information on the use of the mute control function see the MUTEC1 and MUTEC234 pins in Section 5. Pin Description.
4.4
Filter Control (Address 04h)
6 Reserved 0 5 Reserved 0 4 FILT_SEL 0 3 Reserved 0 2 DEM1 0 1 DEM0 0 0 RMP_DN 0
7 Reserved 0
4.4.1
Interpolation Filter Select (FILT_SEL)
Default = 0 0 - Fast roll-off 1 - Slow roll-off Function: This Function allows the user to select whether the interpolation filter has a fast or slow roll off. For filter characteristics please see Section 1.
4.4.2
De-Emphasis Control (DEM)
Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz Function:
20
DS514F2
CS4382
Selects the appropriate digital filter to maintain the standard 15 ms/50 ms digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Figure 39) De-emphasis is only available in Single-Speed Mode.
4.4.3
Soft Ramp-Down Before Filter Mode Change (RMP_DN)
Default = 0 0 - Disabled 1 - Enabled Function: A mute will be performed prior to executing a filter mode change. When this feature is enabled, this mute is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate mute is performed prior to executing a filter mode change. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
4.5
Invert Control (Address 05h)
6 INV_A4 0 5 INV_B3 0 4 INV_A3 0 3 INV_B2 0 2 INV_A2 0 1 INV_B1 0 0 INV_A1 0
7 INV_B4 0
4.5.1
Invert Signal Polarity (INV_XX)
Default = 0 0 - Disabled 1 - Enabled Function: When enabled, these bits will invert the signal polarity of their respective channels.
4.6
Mixing Control Pair 1 (Channels A1 & B1)(Address 06h) Mixing Control Pair 2 (Channels A2 & B2)(Address 09h) Mixing Control Pair 3 (Channels A3 & B3)(Address 0Ch) Mixing Control Pair 4 (Channels A4 & B4)(Address 0Fh)
6 PxATAPI4 0 5 PxATAPI3 1 4 PxATAPI2 0 3 PxATAPI1 0 2 PxATAPI0 1 1 PxFM1 0 0 PxFM0 0
7 Px_A=B 0
4.6.1
Channel A Volume = Channel B Volume (A=B)
Default = 0 0 - Disabled 1 - Enabled Function: The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are determined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ignored when this function is enabled.
DS514F2
21
CS4382
4.6.2 ATAPI Channel Mixing and Muting (ATAPI)
Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4382 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 3 and Figure 41 for additional information.
ATAPI4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ATAPI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
ATAPI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
ATAPI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
AOUTAx MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL [(aL+bR)/2] [(aL+bR)/2] [(bL+aR)/2] [(aL+bR)/2]
AOUTBx MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(bL+aR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2]
Table 3. ATAPI Decode
22
DS514F2
CS4382
4.6.3 Functional Mode (FM)
Default = 00 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) 11 - Direct Stream Digital Mode Function: Selects the required range of input sample rates or DSD Mode. When DSD Mode is selected for any channel pair then all pairs will switch to DSD Mode.
4.7
Volume Control (Addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh, 10h, 11h)
6 xx_VOL6 0 5 xx_VOL5 0 4 xx_VOL4 0 3 xx_VOL3 0 2 xx_VOL2 0 1 xx_VOL1 0 0 xx_VOL0 0
7 xx_MUTE 0
4.7.1
Mute (MUTE)
Default = 0 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero Cross bits. The MUTEC pins will go active during the mute period according to the MUTEC register.
4.7.2
Volume Control (xx_VOL)
Default = 0 (No attenuation) Function: The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments from 0 to -127 dB. Volume settings are decoded as shown in Table 4. The volume changes are implemented as dictated by the Soft and Zero Cross bits. All volume settings less than -127 dB are equivalent to enabling the MUTE bit. Binary Code 0000000 0010100 0101000 0111100 1011010 Decimal Value 0 20 40 60 90 Volume Setting 0 dB -20 dB -40 dB -60 dB -90 dB
Table 4. Example Digital Volume Settings
DS514F2
23
CS4382
4.8 Chip Revision (Address 12h)
7 PART3 1 6 PART2 0 5 PART1 1 4 PART0 0 3 Reserved 2 Reserved 1 Reserved 0 Reserved -
4.8.1
Part Number ID (PART) [Read Only]
1010 - CS4382 Function: This read-only register can be used to identify the model number of the device.
24
DS514F2
CS4382 5. PIN DESCRIPTION
M3(DSD_SCLK) AOUTB1+ AOUTA1+ DSDB2 DSDA3 DSDB3 DSDA4 DSDB4 AOUTA1MUTEC1 AOUTB136 35 34 33 32
4 8 4 7 4 6 4 5 4 4 4 3 4 2 41 4 0 3 9 38 3 7 DSDA2 DSDB1 DSDA1 VD GND MCLK LRCK1(DSD_EN) SDIN1 SCLK1 LRCK2 SDIN2 SCLK2 1 2 3 4 5 6 7 8 9 10 11 12 AOUTA2AOUTA2+ AOUTB2+ AOUTB2VA GND AOUTA3AOUTA3+ AOUTB3+ AOUTB3AOUTA4AOUTA4+
VLS
CS4382
31 30 29 28 27 26 25
1 3 1 4 1 5 1 6 1 7 1 8 1 9 20 2 1 2 2 23 2 4 M0(AD0/CS ) M1(SDA/CDIN) MUTEC234 M2(SCL/CCLK) AOUTB4+ RST AOUTB4SDIN3 SDIN4 FILT+ VLC VQ
Pin Name
VD GND MCLK LRCK1 LRCK2 SDIN1 SDIN2 SDIN3 SDIN4 SCLK1 SCLK2 VLC RST FILT+
#
4 5 31 6 7 10 8 11 13 14 9 12 18 19 20
Pin Description
Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operating Conditions for appropriate voltages. Ground (Input) - Ground reference. Should be connected to analog ground. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Table 5 illustrates several standard audio sample rates and the required master clock frequency. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs. Serial Audio Data Input (Input) - Input for two's complement serial audio data.
Serial Clock (Input) - Serial clock for the serial audio interface. Control Port Power (Input) - Determines the required signal level for the control port. Refer to the Recommended Operating Conditions for appropriate voltages. Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Requires the capacitive decoupling to analog ground, as shown in the Typical Connection Diagram. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source impedance and any current drawn from this pin will alter device performance. However, VQ can be used to bias the analog circuitry assuming there is no AC signal component and the DC current is less than the maximum specified in the Analog Characteristics and Specifications section.
VQ
21
DS514F2
25
CS4382
Pin Name
MUTEC1 MUTEC234 AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,AOUTA4 +,AOUTB4 +,VA VLS
#
41 22
Pin Description
Mute Control (Output) - The Mute Control pins go high during power-up initialization, reset, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. These pins are intended to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any single supply system. The use of external mute circuits are not mandatory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
39, 40 38, 37 35, 36 34, 33 Differential Analog Output (Output) - The full scale differential analog output level is specified in the 29, 30 Analog Characteristics specification table. 28, 27 25, 26 24, 23 32 43
Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Operating Conditions for appropriate voltages. Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages. Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up resistor to the logic interface voltage in IC Mode as shown in the Typical Connection Diagram. Serial Control Data (Input/Output) - SDA is a data I/O line in IC Mode and requires an external pull-up resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDIN is the input data line for the control port interface in SPI Mode. Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC Mode; CS is the chip select signal for SPI format.
Control Port Definitions
SCL/CCLK 15
SDA/CDIN
16
AD0/CS
17
Stand-Alone Definitions
M0 M1 M2 M3 DSD_SCLK DSD_EN DSDA1 DSDB1 DSDA2 DSDB2 DSDA3 DSDB3 DSDA4 DSDB4 17 16 15 42 42 7 3 2 1 48 47 46 45 44
Mode Selection (Input) - Determines the operational mode of the device as detailed in Tables 6 and 7.
DSD Definitions
DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital audio interface. DSD-Enable (Input) - When held at logic `1' the device will enter DSD Mode (Stand-Alone Mode only).
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.
26
DS514F2
CS4382
Mode (sample-rate range) MCLK Ratio Single-Speed (4 to 50 kHz) Sample Rate (kHz) 32 44.1 48 MCLK (MHz) Control port only modes 1024x* 32.7680 45.1584 49.1520 512x* 32.7680 45.1584 49.1520 256x* 45.1584 49.1520
256x 384x 512x 768x* 8.1920 12.2880 16.3840 24.5760 11.2896 16.9344 22.5792 33.8688 12.2880 18.4320 24.5760 36.8640 MCLK Ratio 128x 192x 256x 384x 64 8.1920 12.2880 16.3840 24.5760 Double-Speed (50 to 100 kHz) 88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640 MCLK Ratio 64x 96x 128x 192x 176.4 11.2896 16.9344 22.5792 33.8688 Quad-Speed (100 to 200 kHz) 192 12.2880 18.4320 24.5760 36.8640 Note: *These modes are only available in Control Port Mode by setting the MCLKDIV bit = 1. Table 5. Common Clock Frequencies M1 (DIF1)
0 0 1 1
M0 (DIF0)
0 1 0 1
DESCRIPTION
Left Justified, up to 24-bit data IS, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data
FORMAT
0 1 2 3
FIGURE
33 34 35 36
Table 6. Digital Interface Format, Stand-Alone Mode Options
M3
0 0 1 1
M2 (DEM)
0 1 0 1
DESCRIPTION
Single-Speed without De-Emphasis (4 to 50 kHz sample rates) Single-Speed with 44.1 kHz De-Emphasis; see Figure 39 Double-Speed (50 to 100 kHz sample rates) Quad-Speed (100 to 200 kHz sample rates)
Table 7. Mode Selection, Stand-Alone Mode Options DSD_Mode (LRCK1)
1 1 1 1 1 1 1 1
M2
0 0 0 0 1 1 1 1
M1
0 0 1 1 0 0 1 1
M0
0 1 0 1 0 1 0 1
DESCRIPTION
64x oversampled DSD data with a 4x MCLK to DSD data rate Reserved Reserved Reserved 128x oversampled DSD data with a 2x MCLK to DSD data rate Reserved Reserved Reserved
Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options
DS514F2
27
CS4382 6. APPLICATIONS
6.1 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4382 requires careful attention to power supply and grounding arrangements to optimize performance. Figures 5 and 6 show the recommended power arrangement with VA, VD, VLS and VLC connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin (see Section 1. Characteristics and Specifications for recommended voltages).
6.2
PCM Mode Select
The CS4382 operates in one of three PCM oversampling modes based on the input sample rate. Mode selection is determined by the M3 and M2 pins in Stand-Alone Mode or the FM bits in Control Port Mode. Single-Speed Mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. DoubleSpeed Mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. QuadSpeed Mode supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x. The PCM digital interface format is determined by the M1 and M0 pins in Stand-Alone Mode or the DIF bits in Control Port Mode. In Stand-Alone Mode, the states of these pins are continually scanned for changes; however, the mode should only be changed while the device is in reset (RST pin low) to ensure proper switching from one mode to another.
6.3
Recommended Power-Up Sequence
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control port is reset to its default settings and VQ will remain low. 2. Bring RST high. The device will remain in a low power state with VQ low and will initiate the Stand-Alone power-up sequence. The control port will be accessible at this time. If Control Port operation is desired, write the CPEN bit prior to the completion of the Stand-Alone power-up sequence, approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). Writing this bit will halt the Stand-Alone power-up sequence and initialize the control port to its default settings. The desired register settings can be loaded while keeping the PDN bit set to 1. 3. If Control Port Mode is selected via the CPEN bit, set the PDN bit to 0 which will initiate the power-up sequence.
6.4
Analog Output and Filtering
The application note "Design Notes for a 2-Pole Filter with Differential Input" discusses the second-order Butterworth filter and differential to single-ended converter which was implemented on the CS4382 evaluation board, CDB4382, as seen in Figure 42. The CS4382 does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.
6.5
Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS4382 incorporates selectable interpolation filters for each mode of operation. A "fast" and a "slow" roll-off filter is available in each of Single, Double, and Quad-Speed modes. These filters have been designed to accommodate a variety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the control port section for more details).
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When in Stand-Alone Mode, only the "fast" roll-off filter is available. Filter specifications can be found in Section 1, and filter response plots can be found in Figures 9 to 32.
6.6
Clock Source Selection
The CS4382 has two serial clock and two left/right clock inputs. The SDINxCLK bits in the control port allow the user to set which SCLK/LRCK pair is used to latch the data for each SDINx pin. The clocks applied to LRCK1 and LRCK2 must be derived from the same MCLK and must be exact frequency multiples of each other as specified in the "Switching Characteristics" on page 9. When using both SCLK1/LRCK1 and SCLK2/LRCK2, if either SCLK/LRCK pair loses synchronization then both SCLK/LRCK pairs will go through a retime period where the device is re-evaluating clock ratios. During the retime period all DAC pairs are temporarily inactive, outputs are muted, and the mute control pins will go active according to the MUTEC register. If unused, SCLK2 and LRCK2 should be tied static low and SDINx bits should all be set to SCLK1/LRCK1. In Stand-Alone Mode, all DAC pairs use SCLK1 and LRCK1 for timing and SCLK2/LRCK2 should be tied to ground.
6.7
Using DSD Mode
In Stand-Alone Mode, DSD operation is selected by holding DSD_EN(LRCK1) high and applying the DSD data and clocks to the appropriate pins. The M2:0 pins set the expected DSD rate and MCLK ratio. In Control Port Mode, the FM bits set the device into DSD Mode (DSD_EN pin is not required to be held high). The DIF register then controls the expected DSD rate and MCLK ratio. To access the full range of DSD clocking modes (other than 64x DSD 4x MCLK and 128x DSD 2x MCLK) the following additional register sequence needs to be written: 99h to register 00h 80h to register 1Ah 00h to register 00h When exiting DSD Mode the following additional sequence needs to be written: 99h to register 00h 00h to register 1Ah 00h to register 00h During DSD operation, the PCM related pins should either be tied low or remain active with clocks (except LRCK1 in Stand-Alone Mode). When the DSD related pins are not being used they should either be tied static low, or remain active with clocks (except M3 in Stand-Alone Mode).
7. CONTROL PORT INTERFACE
The control port is used to load all the internal settings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The CS4382 has MAP auto increment capability, enabled by the INCR bit in the MAP register, which is the MSB. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment after each byte is written from register 01h to 08h and then from 09h and 11h, allowing block reads or writes of successive registers in two separate sections (the counter will not auto-increment to register 09h from register 08h).
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CS4382
7.1 Enabling the Control Port
On the CS4382 the control port pins are shared with stand-alone configuration pins. To enable the control port, the user must set the CPEN bit. This is done by performing a IC or SPI write. Once the control port is enabled, these pins are dedicated to control port functionality. To prevent audible artifacts, the CPEN bit (see Section 4.1.1) should be set prior to the completion of the Stand-Alone power-up sequence, approximately 1024 LRCK cycles. Writing this bit will halt the Stand-Alone power-up sequence and initialize the control port to its default settings. Note, the CP_EN bit can be set any time after RST goes high; however, setting this bit after the Stand-Alone power-up sequence has completed can cause audible artifacts.
7.2
Format Selection
The control port has 2 formats: SPI and IC, with the CS4382 operating as a slave device. If IC operation is desired, AD0/CS should be tied to VLC or GND. If the CS4382 ever detects a high to low transition on AD0/CS after power-up and after the control port is activated, SPI format will be selected.
7.3
IC Format
In IC Format, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with a clock to data relationship as shown in Figure 7. The receiving device should send an acknowledge (ACK) after each byte received. There is no CS pin. Pin AD0 forms the partial chip address and should be tied to VLC or GND as required. The upper 6 bits of the 7 bit address field must be 001100. Note: MCLK is required during all IC transactions. Please see "References" on page 40 to obtain additional information on the IC Bus specification or visit http://www.semiconductors.philips.com.
7.3.1
Writing in IC Format
To communicate with the CS4382, initiate a START condition of the bus. Next, send the chip address. The eighth bit of the address byte is the R/W bit (low for a write). The next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be written. To write multiple registers, continue providing a clock and data, waiting for the CS4382 to acknowledge between each byte. To end the transaction, send a STOP condition.
7.3.2
Reading in IC Format
To communicate with the CS4382, initiate a START condition of the bus. Next, send the chip address. The eighth bit of the address byte is the R/W bit (high for a read). The contents of the register pointed to by the MAP will be output after the chip address. To read multiple registers, continue providing a clock and issue an ACK after each byte. To end the transaction, send a STOP condition.
7.4
SPI Format
In SPI format, CS is the CS4382 chip select signal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller and the chip address is 0011000. CS, CCLK and CDIN are all inputs and data is clocked in on the rising edge of CCLK. Note: The CS4382 is write-only when in SPI format.
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7.4.1 Writing in SPI
Figure 8 shows the operation of the control port in SPI format. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address and must be 0011000. The eighth bit is a read/write indicator (R/W), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into register designated by the MAP. To write multiple registers, keep CS low and continue providing clocks on CCLK. End the read transaction by setting CS high.
N o te 1 SDA
001100 ADDR AD0 R /W ACK D ATA 1 -8 ACK DATA 1 -8 ACK
SCL S ta rt S to p
N o te : If o p e ra tio n is a w rite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o in te r, M A P .
Figure 7. Control Port Timing, IC Format
CS CCLK
C H IP ADDRESS
C D IN
0011000
R /W
MAP
MSB
DATA
LSB
b y te 1
M A P = M e m o r y A d d r e s s P o in te r
b y te n
Figure 8. Control Port Timing, SPI Format
7.5
Memory Address Pointer (MAP)
7 INCR 0 6 Reserved 0 5 Reserved 0 4 MAP4 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 0
7.5.1
INCR (Auto Map Increment Enable)
Default = `0' 0 - Disabled 1 - Enabled Note: When Auto Map Increment is enabled, the register must be written it two separate blocks: from register 01h to 08h and then from 09h and 11h. The counter will not auto-increment to register 09h from register 08h
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CS4382
7.5.2 MAP4-0 (Memory Address Pointer)
Default = `00000'
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CS4382 8. FILTER PLOTS
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 9. Single-Speed (fast) Stopband Rejection
0
Figure 10. Single-Speed (fast) Transition Band
0.02
1
0.015
2
0.01
3
0.005 Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 11. Single-Speed (fast) Transition Band (detail)
0
Figure 12. Single-Speed (fast) Passband Ripple
0
20
20
Amplitude (dB)
40
60
Amplitude (dB)
0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 1
40
60
80
80
100
100
120
120
0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 13. Single-Speed (slow) Stopband Rejection
Figure 14. Single-Speed (slow) Transition Band
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CS4382
0
0.02
1
0.015
2
0.01
3
0.005
Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.02
0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 15. Single-Speed (slow) Transition Band (detail)
0
Figure 16. Single-Speed (slow) Passband Ripple
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 17. Double-Speed (fast) Stopband Rejection
0
Figure 18. Double-Speed (fast) Transition Band
0.02
1
0.015
2
0.01
3
Amplitude (dB)
5
Amplitude (dB)
4
0.005
0
6
0.005
7
0.01
8
9
0.015
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 19. Double-Speed (fast) Transition Band (detail)
Figure 20. Double-Speed (fast) Passband Ripple
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CS4382
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
Figure 21. Double-Speed (slow) Stopband Rejection
0
Figure 22. Double-Speed (slow) Transition Band
0.02
1
0.015
2
0.01
3
0.005
Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
0.02
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15 0.2 Frequency(normalized to Fs)
0.25
0.3
0.35
Figure 23. Double-Speed (slow) Transition Band (detail)
0
Figure 24. Double-Speed (slow) Passband Ripple
0
20
20
40 Amplitude (dB)
Amplitude (dB)
40
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
Figure 25. Quad-Speed (fast) Stopband Rejection
Figure 26. Quad-Speed (fast) Transition Band
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CS4382
0
0.2
1
0.15
2
0.1
3
0.05
Amplitude (dB)
Amplitude (dB) 0.05 0.1 0.15 0.2
4
5
0
6
7
8
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0
0.05
0.1 0.15 Frequency(normalized to Fs)
0.2
0.25
Figure 27. Quad-Speed (fast) Transition Band (detail)
0
Figure 28. Quad-Speed (fast) Passband Ripple
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.1
0.2
0.3
0.4 0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
0.9
Figure 29. Quad-Speed (slow) Stopband Rejection
0
Figure 30. Quad-Speed (slow) Transition Band
0.02
1
0.015
2
0.01
3
0.005 Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.02
0.04 0.06 0.08 Frequency(normalized to Fs)
0.1
0.12
Figure 31. Quad-Speed (slow) Transition Band (detail)
Figure 32. Quad-Speed (slow) Passband Ripple
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CS4382 9. DIAGRAMS
LRCK SCLK Left Channel Right Channel
SDINx
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 33. Format 0 - Left Justified up to 24-bit Data
LRCK SCLK
Left Channel
Right Channel
SDINx
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 34. Format 1 - IS up to 24-bit Data
LRCK
Left Channel
Right Channel
SCLK
SDINx
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 35. Format 2 - Right Justified 16-bit Data
LRCK
Left Channel
Right Channel
SCLK
SDINx
0
23 22 21 20 19 18
76543210
23 22 21 20 19 18
76543210
32 clocks
Figure 36. Format 3 - Right Justified 24-bit Data
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CS4382
LRCK Right Channel
Left Channel
SCLK
SDINx
10
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 37. Format 4 - Right Justified 20-bit Data
LRCK
Left Channel
Right Channel
SCLK
SDINx
10
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 38. Format 5 - Right Justified 18-bit Data
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 39. De-Emphasis Curve
L Channel Pair x Control R
DAC
AOUTAx+ AOUTAx-
SDINx
DAC
AOUTBx+ AOUTBx-
Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, 3, or 4)
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DS514F2
CS4382
Left Channel Audio Data
A Channel Volume Control
MUTE
Aout Ax
SDINx
Right Channel Audio Data
B Channel Volume Control
MUTE
AoutBx
Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)
Figure 42. Recommended Output Filter
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39
CS4382 10.PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES171991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C.
11.REFERENCES
1. How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. CDB4382 Evaluation Board Datasheet 3. Design Notes for a 2-Pole Filter with Differential Input by Steven Green. Cirrus Logic Application Note AN48, available at http:www.cirrus.com 4. The IC-Bus Specification: Version 2.0 Philips Semiconductors, December 1998. http://www.semiconductors.philips.com
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CS4382 12.PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
INCHES NOM
0.055 0.004 0.009 0.354 0.28 0.354 0.28 0.020 0.24 4
DIM
A A1 B D D1 E E1 e* L
MIN
--0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000
MAX
0.063 0.006 0.011 0.366 0.280 0.366 0.280 0.024 0.030 7.000
MIN
--0.05 0.17 8.70 6.90 8.70 6.90 0.40 0.45 0.00
MILLIMETERS NOM
1.40 0.10 0.22 9.0 BSC 7.0 BSC 9.0 BSC 7.0 BSC 0.50 BSC 0.60 4
MAX
1.60 0.15 0.27 9.30 7.10 9.30 7.10 0.60 0.75 7.00
* Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS022
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CS4382 13.ORDERING INFORMATION
Product Description Package Pb-Free
YES -
Grade
Temp Range
Container
Tray Tape and Reel -
Order #
CS4382-KQZ CS4382-KQZR CDB4382
114 dB, 192 kHz 848-pin CS4382 channel D/A Converter LQFP CDB4382 CS4382 Evaluation Board
Commercial -10C to +70C -
14.REVISION HISTORY
Release Changes
Removed -BQ ordering option Corrected specifications for Full Scale Differential Output Voltage Updated Table 2 on page 18 Updated Section 6.7 "Using DSD Mode" on page 29 Updated legal text Corrected DAC Pair Disable register description in Section 4.1.4 Added note to Digital Interface Format in Section 4.2.1 Added PCM mode format changeable only in reset to Section 6.2 Updated Package Thermal Resistance in "Power and Thermal Characteristics" on page 6
F1
F2
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. IC is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.
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